Presentation Title

Transistor Design and Modeling in Nanoelectronics Fabrication

Faculty Mentor

Albert Wang

Start Date

18-11-2017 2:15 PM

End Date

18-11-2017 3:15 PM

Location

BSC-Ursa Minor 147

Session

Poster 3

Type of Presentation

Poster

Subject Area

engineering_computer_science

Abstract

In the realm of nanoelectronics, there is a strong desire to dimension shrinking for better performance, specifically in regards to transistors. Utilizing the Sentaurus software, design and simulation of P-N junctions and MOSFET devices was conducted aiming for visible light communications system applications. The Sentaurus Structural Editor (SDE) was implemented to create a 3D-model for device simulation. After applying the appropriate doping to the silicon channel and creating the mesh required to simulate the activity within the transistor using SDE, the program Inspect was used to simulate varying voltage levels across the gate and drain. Experimental results revealed that as the gate voltage increases, the total current reaches higher saturation levels. Sentaurus Workbench was employed to combine the 3D model and inspect, resulting in a successfully simulated MOSFET. Through the process of doping, impurities were added to silicon via two methods: P-type which is silicon with added boron impurities, or other Group III elements, creating free “holes” within the silicon structure where electrons should be, and N-type, which is doped with arsenic, or any Group IV element, to create free electrons. When the two types of semiconductors are combined, a P-N junction is created. The holes and electrons near the junction mix until equilibrium is reached, forming the space charged region, along with an electric field in the direction from the N-type to P-type regions. Depending on the voltages applied to the N- or P-type side of the junction, a current will flow through in one direction, or a potential barrier that forbids current from flowing. When manufacturing the transistors, layers were added using Chemical Vapor Deposition and removed using an acid rinse, followed by a process called Chemical Mechanical Polish, which is accomplished through the use of a chemical slurry and a fine polisher spun to thin the layer. The polymer photoresist was used to keep desired sections of the layers. During the acid rinse, the altered photoresist dissolved, leaving the unaltered remaining and the layer underneath it preserved. After stripping the photoresist, layering of the wafer was continued. To test our transistor, a device with three fragile needles was used to make contact with the source, drain, and gate of a transistor. Then, voltages are applied and a plot of the current running through the transistor was obtained. After placing the wafer onto a probe station, inspection is conducted. A microscope connects to a computer terminal to view the wafer on a microscopic level, with a joystick to assess different sections of the wafer. After careful evaluation and testing, the transistor design is completed.

Sponsor: NSF IRES

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Nov 18th, 2:15 PM Nov 18th, 3:15 PM

Transistor Design and Modeling in Nanoelectronics Fabrication

BSC-Ursa Minor 147

In the realm of nanoelectronics, there is a strong desire to dimension shrinking for better performance, specifically in regards to transistors. Utilizing the Sentaurus software, design and simulation of P-N junctions and MOSFET devices was conducted aiming for visible light communications system applications. The Sentaurus Structural Editor (SDE) was implemented to create a 3D-model for device simulation. After applying the appropriate doping to the silicon channel and creating the mesh required to simulate the activity within the transistor using SDE, the program Inspect was used to simulate varying voltage levels across the gate and drain. Experimental results revealed that as the gate voltage increases, the total current reaches higher saturation levels. Sentaurus Workbench was employed to combine the 3D model and inspect, resulting in a successfully simulated MOSFET. Through the process of doping, impurities were added to silicon via two methods: P-type which is silicon with added boron impurities, or other Group III elements, creating free “holes” within the silicon structure where electrons should be, and N-type, which is doped with arsenic, or any Group IV element, to create free electrons. When the two types of semiconductors are combined, a P-N junction is created. The holes and electrons near the junction mix until equilibrium is reached, forming the space charged region, along with an electric field in the direction from the N-type to P-type regions. Depending on the voltages applied to the N- or P-type side of the junction, a current will flow through in one direction, or a potential barrier that forbids current from flowing. When manufacturing the transistors, layers were added using Chemical Vapor Deposition and removed using an acid rinse, followed by a process called Chemical Mechanical Polish, which is accomplished through the use of a chemical slurry and a fine polisher spun to thin the layer. The polymer photoresist was used to keep desired sections of the layers. During the acid rinse, the altered photoresist dissolved, leaving the unaltered remaining and the layer underneath it preserved. After stripping the photoresist, layering of the wafer was continued. To test our transistor, a device with three fragile needles was used to make contact with the source, drain, and gate of a transistor. Then, voltages are applied and a plot of the current running through the transistor was obtained. After placing the wafer onto a probe station, inspection is conducted. A microscope connects to a computer terminal to view the wafer on a microscopic level, with a joystick to assess different sections of the wafer. After careful evaluation and testing, the transistor design is completed.

Sponsor: NSF IRES